The Nano Thin Film Deposition is a session to focus on the cutting-edge research results and innovative insights related to thin film materials, processing, and device manufacturing for the emerging memory and logic semiconductor applications. With the semiconductor market continuously advancing towards higher density and enhanced performance, there is a growing demand for advanced nanoscale thin film processing to facilitate the integration of alternative materials and complex 3D device structures. Therefore, the primary objective of this session is to introduce the latest research outcomes on advanced thin film technologies, surface science, and inorganic/organic chemistry for the development of new materials and their applications in devices. Additionally, theoretical simulations of thin film deposition reactions and the development of chemical precursors will be discussed during this session. This symposium serves as a platform for researchers from diverse fields, including materials science, surface science, inorganic chemistry, condensed matter physics, electrical engineering, and quantum information science, to exchange the latest research findings and pioneer new frontiers in thin film deposition research.

• Advanced thin films for semiconductor applications
• Chemical and physical-based deposition for semiconductors
• Atomic layer deposition and its semiconductor applications
• Area selective deposition method for future semiconductors
• Precursor development for CVD and ALD
• Emerging applications of nano thin films in semiconductors
• Modelling, simulation, and theoretical studies of nano thin films
• Other topics related with semiconductor thin films

The CMP & Cleaning session will focus and discuss the research on novel functional CMP process, CMP slurry, post cleaning, wet etching, surface preparation and wafer cleaning for scaling-down logic and memory devices, being able to perform high removal rate, high selectivity, dishing-free, erosion-less, scratch-less, and remaining particle-less CMPs and highly selective etching and cleaning processes. Several CMP mechanisms will be reviewed by the applied surface science such as dynamic mechanical and chemical behavior. Beyond conventional CMP abrasives such as colloidal silica and zirconia etc., novel CMP abrasives such as core/shell abrasives and chemical deliverable abrasives will be introduced. In addition, this session covers a wide range of topics related to the science and technology of contaminants removal and surface preparation of various semiconductors such as Si, Ge, SiGe, and III-V, FEOL and BEOL cleaning technologies, pattern collapse prevention, ; photoresist and residue removal of 3D device structures. Also, wafer characterization, evaluation, and monitoring techniques including cleaning process equipment and hardwares will be discussed.

• CMP process, CMP slurry, post-cleaning process for STI, ILD, poly silicon, nitride, tungsten, copper, amorphous carbon, and GeSbTe film planarization.
• Super-fine (abrasive dimeter: < 5 nm) ceria CMP slurry, related post cleaning, and CMP process application.
• Extremely high surface topography (i.e., > 1 μm) CMP slurry and process.
• Core/shell abrasive based CMP slurry and CMP performance.
• Cleaning technologies for maintaining high selectivity at extremely high aspect ratios
• Chemical and physical phenomena in cleaning process
• New cleaning method and concept for fine 3D structures
• Eco-friendly cleaning chemicals and processes

As the device integration is increased continuously, the critical dimension of semiconductor device has decreased to a few nanometers and the device structure is changing from two dimensional (2D) structures to three dimensional (3D) structures. Due to the complexity of the device fabrication and the use of various materials for the semiconductor devices, the etching technology has become one of the most difficult technologies for next generation semiconductor device fabrication requiring low damage etching, highly selective etching, high aspect ratio etching, etc. on 2D and 3D structured materials. In this session, the advanced etch technologies such as ALE, cyclic etching, pulsed plasma etching, etching with low GWP materials, etc. which are required for the next generation semiconductor device fabrication will be presented. The researchers and engineers working in the etching of the semiconductor and display materials are welcome to this session, and encouraged to attend and present their works in this session.

• New Etching process
• Etching mechanism
• Plasma diagnostics & monitoring
• Plasma sources for etching

The field of lithography faces a challenging task of extending into ever-shrinking generations while remaining cost-effective and manufactural. State-of-the-art processes such as immersion lithography and multiple patterning have been implemented to address this challenge, with EUV lithography making significant progress and starting to be employed for mass production. Moreover, a high-NA EUV tool is expected to be delivered soon, which is poised to further enhance the capabilities of EUV lithography. To complement these efforts, the lithography community is actively pursuing alternative patterning approaches and complementary solutions. Success in this field necessitates unique interdisciplinary interactions and coordinated efforts between lithographers, layout designers, materials scientists, and metrology/process control engineers to enable cost-efficient patterning solutions. This symposium covers a broad spectrum of lithography and patterning topics, attracting participants from diverse backgrounds to share and learn about state-of-the-art lithographic tools, resists, metrology, materials, design, process integration, and novel approaches. The symposium also fosters provocative discussions and seminars to address current issues in the field, such as extending current methods, exploring alternative approaches, and identifying new ways to complement existing technologies.

• EUV Lithography : EUV scanner, EUV tool, EUV mask, EUV OPC, EUV Patterning material
• Patterning Materials: EUV resist, photoresists for optical lithography, materials for alternative lithography, photopatternable functional materials
• Nano Fabrication for next generation optical devices: Nanoprinting for optical metasurfaces, printable nanolasers
• Alternative Lithography: 3D Patterning, Imprinting, Self-assemble, non-conventional lithography
• Layout optimization & Computational Lithography: DTCO(design technology co-optimization), DFM(design for manufacturing), SMO(source mask optimization)
• Advanced Metrology and Inspection: optical inspection, interference microscopy, advanced process control, overlay metrology, computational metrology
• Applications and Related Emerging Topics

As the demand for low-power, multi-functional semiconductors continues to grow, the industry faces a challenge to find alternative materials, processes, devices, and systems to meet these demands. One approach to addressing these challenges is through advanced packaging technology, which has become another driving force for semiconductor technology development. Advanced packaging technology involves creating packages or housings for integrated circuits that go beyond traditional chip-scale packaging and includes technologies such as fan-out wafer-level packaging (FO-WLP), 3D packaging, and heterogeneous integration.

Heterogeneous integration, which includes 3D IC, system-in-package, and monolithic 3D (M3D), has garnered much interest in the industry due to its potential to improve device performance, increase functionality, and reduce form factor. In this regard, the heterogeneous integration packaging will focus on advanced packaging materials, processes, and integrations for a range of applications such as mobile, high-performance computing (HPC), automotive, 5G, health, and chiplets.

The session will cover a wide range of topics related to heterogeneous integration, including the latest developments in advanced packaging materials such as underfill, die attach, and encapsulants; new packaging processes such as through-silicon vias (TSVs), wafer-level bonding, and fan-out panel-level packaging (FO-PLP); and innovative integration approaches such as system-in-package (SiP) and monolithic 3D (M3D). Through these discussions, we aim to promote knowledge sharing, identify key challenges, and explore solutions that will drive the next generation of advanced packaging technology for the semiconductor industry.

• Advanced packaging for heterogeneous integration
• 2.5D and 3D packaging technology
• Fan-out and Fan-In technology
• Hybrid and direct bonding for 3D integration
• Thermal/mechanical simulation & characterization
• Advanced device and system using heterogeneous integration
• Monolithic 3D integration
• Topics related with heterogeneous integration

The advancement in IC manufacturing has introduced novel fabrication techniques such as three-dimensional stacked integrated circuit (3DS-IC) fabrication and emerging devices including PIM, ferroelectrics, and new types of transistors. However, these new techniques have presented challenges for both in-line and ex-situ metrology and characterization.
The production of 3DS-ICs requires complex processes such as high-aspect ratio through-silicon vias (TSVs), thin wafer handling and processing, wafer thinning, and bonding of thin wafers with complex patterned surfaces, each of which pose unique metrology challenges. Additionally, 3D gate stack integration creates atomic scale defect control issues that were not previously encountered in planar FETs.

Moreover, emerging devices like ferroelectric FETs, TFETs, and NCFETs, developed for PIM and steep switching MOSFETs, demand frontier metrology for ultrathin materials and interfaces. Effective process monitoring metrology and nano-scale particles and contamination control are also critical to achieve high device-to-device and lot-to-lot uniformity and target device properties.

Therefore, the purpose of this symposium is to introduce the latest research results on various nano-scale analysis and process modeling on thin films, interfaces, particles, defects, and contaminations in advanced IC manufacturing including but not limited to 3D device integration and emerging devices and materials as well as process diagnosis and monitoring metrology.

• Topics related with physical and chemical analysis of 3D device integration
• Topics related with physical and chemical analysis of nano-scale particles and defects
• Topics related with chemical analysis of contaminations on organic and inorganic materials
• Topics related with MI in the emerging semiconductor process
• Topics related with diagnosis for control semiconductor process

In this session, a wide range of topics related to the technological value-chain of power devices based on advanced Si and wide bandgap semiconductor will be discussed. Regarding materials for power devices, presentation will cover the substrate and epitaxial layer growth of SiC, GaN, Ga2O3, and device-grade diamond growth. The session will focus on novel device structure design and fabrication technology to achieve high Figure of Merit and gate driving technology for reliable, high-speed switching. Research on the reliability and ruggedness of power devices and modules, which have recently gained increasing attention due to their expanded application in electric vehicles, national defense, and space technologies, will be introduced. Additionally, equipment technology for power device manufacturing will be discussed as an important topic in this session.

• Substrate and epitaxial layer growth of wide bandgap compound semiconductor
• Fabrication process and manufacturing equipment technology for power devices
• Novel device design, TCAD simulation and device physics
• Measurement and characterization of power devices and materials
• Device reliability and ruggedness for harsh environment
• Gate driving circuit and technology for robust driving of Power Module
• Materials, novel manufacturing method and multi-physics analysis of Power Module
• Power Electronic System employing wide bandgap power transistor

The Carbon Neutrality in Semiconductor Industry is a session designed to present diverse research outputs related with carbon neutrality in semiconductor industry. Recognition of ever-growing interests in carbon neutrality in semiconductor industry necessitates high demand for energy efficiency, next-generation etching/deposition process, waste recovery, low GWP material, and life cycle assessment for various processes employed in semiconductor industry and this session can provide an excellent venue to exchange ideas and research works between academia, industry partners, and government officials.

• RE 100/CF 100
• Sustainable etching/deposition process
• Energy efficiency
• Waste recovery
• Low GWP material development
• CO₂ capture and utilization
• Power to X
• Life cycle assessment